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Trace
7.3
Contents of
Trace Window
Based on
Instruction
(ICE50)
As can be seen from Enabling Trace, the contents of the different columns varies with
which instruction is being executed. This section describes how to interpret the contents
of the Trace buffer based on which instruction is being executed.
Some of the explanations are tagged with a number. This number indicates the cycle
number in the instruction execution (important for multi-cycle instructions only). The
term N/A is used when a field does not contain any valuable information.
Table 7-1. Arithmetic and Logic Instructions
Dat.Addr
Instruction
PMem Addr
Reg.Val
RAM_EEADDR
Status
INSTA[0..15]
ADD Rd,Rr
ADC Rd, Rr
[PC[A0..22]
Address of instruction
Address of instruction
1. Address of instruction
RegFileL[0..7]
Result of addition
Result of addition
1. Result of addition, low byte
[0..22]
N/A
N/A
1. N/A
Dat.Val
N/A
N/A
1. N/A
Register
Z,C,N,V,S,H
Z,C,N,V,S,H
ADIW Rdl,K
Z,C,N,V,S
2. Address of next instruction
2. Result of addition, high byte
2. N/A
2. N/A
SUB Rd, Rr
SUBI Rd, K
SBC Rd, Rr
SBCI Rd, K
Address of instruction
Address of instruction
Address of instruction
Address of instruction
1. Address of instruction
Result of subtraction
Result of subtraction
Result of subtraction
Result of subtraction
1. Result of subtraction, low byte
N/A
N/A
N/A
N/A
1. N/A
N/A
N/A
N/A
N/A
1. N/A
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
SBIW Rdl,K
Z,C,N,V,S,H
2. Address of next instruction
2. Result of subtraction, high byte
2. N/A
2. N/A
AND Rd, Rr
ANDI Rd, K
OR Rd,Rr
ORI Rd, K
EOR Rd, Rr
COM Rd
NEG Rd
Address of instruction
Address of instruction
Address of instruction
Address of instruction
Address of instruction
Address of instruction
Address of instruction
Result of logical AND
Result of logical AND
Result of logical OR
Result of logical OR
Result of logical EOR
Result of complement
Result of negation
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Will never appear (is
SBR Rd,K
disassembled to ORI
N/A
N/A
N/A
Z,N,V,S
instruction)
Will never appear (is
CBR Rd,K
disassembled to ANDI
N/A
N/A
N/A
Z,N,V,S
instruction)
INC Rd
DEC Rd
Address of instruction
Address of instruction
Result of incrementation
Result of decrementation
N/A
N/A
N/A
N/A
Z,N,V,S
Z,N,V,S
Will never appear (is
TST Rd
disassembled to AND
N/A
N/A
N/A
Z,N,V,S
instruction)
CLR Rd
Address of instruction
Result (always 0x00)
N/A
N/A
Z,N,V,S
Will never appear (is
SER Rd
disassembled to LDI
N/A
N/A
N/A
N/A
instruction)
7-4
2523A–AVR–11/02
ICE50 User Guide
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